As technology scales down to the nanometer era, manufacturing defects are rapidly becoming a major concern in the design of electronic circuits. In this work, we present a defect-tolerant logic family constructed with CMOS cells. The basic idea of this approach is the construction of logic gates in which the outputs and their complementaries correct each other. We demonstrate, through circuit simulation using CMOS cells from a 65nm industrial process, that the proposed logic turns out to be a good compromise to construct robust circuits under the constraint of limited area overhead.