Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context we introduce a cost-aware methodology for selective hardening of combinational logic cells. The methodology is based on the SPRA algorithm for calculating logical masking, and it is capable to automatically perform a trade-off between reliability improvements and associated costs, providing a list of the most effective candidates for hardening. The methodology is applied to a set of benchmark circuits using costs extracted from an actual standard cell library. The results then show that the methodology is able to diminish the unreliability of circuits in a cost-effective manner.