Hardware/Software Runtime for GPSA Protection in RISC-V Embedded Cores
Environnement d'Exécution Matériel/Logiciel pour la protection GPSA de Coeurs Embarqués RISC-V
Résumé
State-of-the-art hardware countermeasures against fault attacks are based, among others, on control-flow and code integrity checking. Generalized Path Signature Analysis and Continuous Signature Monitoring can assert these integrity properties. However, supporting such mechanisms requires a dedicated compiler flow and does not support indirect jumps. This work proposes a technique based on a hardware/software runtime to generate those signatures while executing unmodified off-the-shelf RISC-V binaries. To the best of our knowledge, this is the first solution for providing this level of protection against fault injection on unmodified binaries. The proposed approach has been implemented on a pipelined processor, and experimental results show an average slowdown of ×3.35 and an area overhead of at least ×1.86 compared to unprotected implementations.
Domaines
Informatique [cs]| Origine | Fichiers produits par l'(les) auteur(s) |
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